LTC4245
17
4245fa
Turn-Off
The switches can be turned off by a variety of condi-
tions.
1. ON pin going low or BD_SEL# going high turns off all
switches.
2. Individual switches can be turned off by resetting
the particular FET On control bit (D0 to D3) through
the serial bus.
3. A variety of fault conditions will turn off all switches
together. These include supply undervoltage,
overcurrent circuit breaker and PGI faults.
4. Writing a logic one into the undervoltage, overcurrent
or PGI fault bits will turn off all switches, if the
corresponding autoretry is not enabled.
Normally the 12V, 5V and 3.3V switches are turned off
with a 1.3mA current pulling down the gate to ground.
V
EEGATE
is pulled through a resistive switch to V
EEIN
. All
supply outputs are also discharged to ground through
internal switches. When any MOSFET is shut off, the
HEALTHY# signal pulls high and LOCAL_PCI_RST# will
be asserted low. Figure 4 shows all supplies being turned
off by BD_SEL# going high.
ON Register and Sequencing
The LTC4245 features an ON register (Table 10) consisting
of four On control bits (D0 to D3) and four On status bits
(D4 to D7). D0 to D3 provide independent on/off control
for each supply through the I
2
C bus. Bits D4 to D7 report
the on status of each supply. Even though a supply may
be commanded to turn-on by setting its On control bit,
it may remain off (On status bit low) because the condi-
tions to turn on, as listed in the Turn-On section, may not
be present.
The sequence control bit, C6, determines whether the four
supply MOSFETs turn-on together or in a xed sequence.
The default state is no sequencing. In this case taking
the ON pin high sets all the four On control bits. If the
start-up conditions are satis ed, all switches will turn on
under the control of a single TIMER and SS cycle. Due to
different input voltage offsets in the current limit ampli er
of each supply, the gate turn-on of all MOSFETs will not
occur at the same moment but will happen in random
order depending on ampli er offset and soft-start ramp
rate. The gate turn-ons will be truly simultaneous only if
SS pin is left open.
If bit C6 is set, then the ON pin going high sets only the
12V On control bit, D0. The 12V back-end supply ramps
up. The end of the TIMER and SS cycle sets the 5V On
control bit, D1, starting the ramp of the 5V supply output.
The end of the 5V timing cycle sets bit D2 and the end of
the 3.3V ramp sets bit D3. In this way, the four On control
APPLICATIO S I FOR ATIO
U
U
U
Figure 4. Normal Turn-Off Waveform
TIME 100ms/DIV
4245 F04
12V
OUT
, 5V
OUT
3V
OUT
, V
EEOUT
, 10V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
LOCAL_PCI_RST#
5V/DIV
Figure 5. Sequential Turn-On Waveform
TIME 50ms/DIV
4245 F05
SS
2.5V/DIV
TIMER
2.5V/DIV
12V
OUT
, 5V
OUT
3V
OUT
, V
EEOUT
, 10V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
LOCAL_PCI_RST#
5V/DIV
bits get set one after another, leading to a 12V, 5V, 3.3V,
12V start-up sequence. Figure 5 illustrates this. If C6 is set
and any of the start-up conditions goes bad, all switches
turn-off, and all On control bits except D0 are reset. This
ensures that the part goes through a sequenced turn-on
during auto-retry. D1 to D3 are also reset when BD_SEL#
goes low with C6 set.
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